Increasing complexity of system design and shorter time-to-market requirements are leading research towards the investigation of hybrid systems including processors enhanced by programmable logic as readily known by those skilled in this technical field. In this respect, reference is made to the work by Young-Don Bae et al., “A Single-Chip Programmable Platform Base on A Multithreaded Processor and Configurable Logic Clusters”, ISSCC 2002 Digest of Technical Papers, pp 336-337, February 2002. Moreover, a further reference which may be considered is an article by Zhang et al., “A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications”, ISSCC 2000 Digest of Technical Papers, pp 68-69,488, February 2000.
At the same time increased costs of mask sets and a shorter time-to-market available for new products are leading to the introduction of systems with a higher degree of programmability and configurability, such as system-on-chips with configurable processors, embedded FPGA and embedded flash memory. Moreover, the availability of an advanced embedded flash technology, based on a NOR architecture, together with innovative IP's, like embedded flash macrocells with special features, is a key factor.
For a better understanding of the present invention reference is also made to the Field Programmable Gate Array (FPGA) technology combining standard processors with embedded FPGA devices. These approaches allow one to configure into the FPGA at deployment time exactly the required peripherals, exploiting temporal reuse by dynamically reconfiguring the instruction set at run time based on the currently executed algorithm.
The existing models for designing FPGA/processor interaction can be grouped in two main categories: 1) the FPGA is a co-processor communicating with the main processor through a system bus or a specific I/O channel; and 2) the FPGA is described as a function unit of the processor pipeline. The first group includes the GARP processor, known from the article by T. Callahan, J. Hauser, and J. Wawrzynek, “The Garp Architecture And C Compiler” IEEE Computer, 33(4): 62-69, April 2000. A similar architecture is provided by the A-EPIC processor that is disclosed in the article by S. Palem and S. Talla, “Adaptive Explicit Parallel Instruction Computing”, Proceedings of the fourth Australian Computer Architecture Conference (ACOAC), January 2001.
In both cases the FPGA is addressed via dedicated instructions, moving data explicitly to and from the processor. Control hardware is kept to a minimum since no interlocks are needed to avoid hazards, but a significant overhead in clock cycles is required to implement communication. When the number of cycles per execution of the FPGA is relatively high, the communication overhead may be considered negligible.
In the commercial world, FPGA suppliers such as Altera Corporation offer digital architectures based on U.S. Pat. No. 5,968,161 to T. J. Southgate, “FPGA Based Configurable CPU Additionally Including Second Programmable Section For Implementation Of Custom Hardware Support”. Other suppliers (Xilinx, Triscend) offer chips containing a processor embedded on the same silicon IC with embedded FPGA logic. See for instance U.S. Pat. No. 6,467,009 to S. P. Winegarden et al., “Configurable Processor System Unit”, assigned to Triscend Corporation.
However, those chips are generally loosely coupled by a high speed dedicated bus, performing as two separate execution units rather than being merged in a single architectural entity. In this manner the FPGA does not have direct access to the processor memory subsystem, which is one of the strengths of academic approaches outlined above. In the second category (FPGA as a function unit) we find architectures commercially known as PRISC, Chimaera and ConCISe.
In all these models, data is read and written directly on the processor register file minimizing overhead due to communication. In most cases, to minimize control logic and hazard handling and to fit in the processor pipeline stages, the FPGA is limited to combinatorial logic only. This severely limits the performance boost that can be achieved.
These approaches represent a significant step toward a low-overhead interface between the two entities. Nevertheless, due to the granularity of FPGA operations and its hardware oriented structure, their approach is still very coarse-grained, reducing the possible resource usage in parallel and again including hardware issues not familiar nor friendly to software compilation tools and algorithm developers.
Thus, a relevant drawback in this approach is often the memory data access bottleneck that often forces long stalls on the FPGA device when fetching on the shared registers enough data to justify its activation.